The present invention relates generally to manufacturing semiconductors and more particularly to patterning semiconductors using masks.
Flash electrically erasable programmable read only memories (Flash EEPROMs) are a class of nonvolatile memory devices that are programmed by hot electron injection and erased by Fowler-Nordheim tunneling.
In the first step of putting such electrical devices on a semiconductor, each memory cell is formed on a semiconductor substrate (i.e., a silicon die or chip), having a heavily doped drain region and a source region embedded therein. The source region further contains a lightly doped deeply diffused region and a more heavily doped shallow diffused region embedded into the substrate. A channel region separates the drain region and the source region. The memory cell further includes a multi-layer structure, commonly referred to as a xe2x80x9cstacked gatexe2x80x9d structure or word line. The stacked gate structure typically includes: a thin gate dielectric or tunnel oxide layer formed on the surface of substrate overlying the channel region; a polysilicon floating gate overlying the tunnel oxide; an interpoly dielectric layer overlying the floating gate; and a polysilicon control gate overlying the interpoly dielectric layer. Additional layers, such as a silicide layer (disposed on the control gate), a poly cap layer (disposed on the silicide layer), and a silicon oxynitride layer (disposed on the poly cap layer) may be formed over the control gate. A plurality of Flash EEPROM cells may be formed on a single substrate.
After the formation of the memory cells, electrical connections, a second step of forming what is commonly known as xe2x80x9ccontactsxe2x80x9d must occur to connect the stack gated structure, the source region and the drain regions to other part of the chip. The contact process starts with the formation of sidewall spacers around the stacked gate structures of each memory cell. An etch-stop layer, typically a nitride material such silicon nitride, is then formed over the entire substrate, including the stacked gate structure, using conventional techniques, such as chemical vapor deposition (CVD). A dielectric layer, generally of oxide, is then deposited over the nitride layer. A layer of photoresist is then placed over the dielectric layer and is photolithographically patterned, exposed, and developed (xe2x80x9cprocessedxe2x80x9d) to form the pattern of contact openings. An anisotropic etch is then used to etch out portions of the dielectric layer to form source and drain contact openings. The contact openings stop at the source and drain regions in the substrate. The photoresist is then stripped, and a conductive material, such as tungsten, is deposited over the dielectric layer and fills the source and drain contact openings to form so-called xe2x80x9cself-aligned contactsxe2x80x9d(conductive contacts). The substrate is then subjected to a chemical-mechanical polishing (CMP) process which removes the conductive material above the dielectric layer to form the conductive contacts through a contact CMP process.
Subsequent steps involving a xe2x80x9cdamascenexe2x80x9d process are used to form local interconnects between the various conductive contacts. An etch-stop layer is formed over the CMP processed surface and a layer of photoresist is then placed over the etch-stop layer and is photolithographically processed to form the pattern of contact openings. Next, a dielectric layer, generally of oxide, is then deposited and a layer of photoresist is then placed over the dielectric layer and is photolithographically processed to form the pattern of first level local interconnect channel openings. An anisotropic etch is then used to etch out portions of the dielectric layer to form the channel openings. The channel openings stop at the etch-stop layer except at the contact openings. The photoresist is then stripped, and a conductive material, such as aluminum or copper, is deposited over the dielectric layer and fills the channel openings. A CMP process removes the conductive material above the dielectric layer to form the local interconnects, or xe2x80x9cwiresxe2x80x9d.
Additional levels of local interconnect and vias connecting the additional levels of local interconnect are formed in xe2x80x9cdual damascenexe2x80x9d processes which are substantially the same as described above with the exception that certain etching steps and conductive material filling steps are combined.
The use of photolithography and photoresist is common to each of these various processes. As semiconductor devices have shrunk in size, the industry has turned towards deep ultraviolet (DUV) lithography as a photolithographic exposure process to pattern openings in sub-0.35 micron line geometry semiconductor devices.
A major obstacle to the miniaturization of semiconductors is the effect of reflectivity in the DUV lithographic and conventional i-line lithographic processes. Reflections occur at the junctions of materials and are influenced in part by the thickness of materials. Because the precision of the photolithographic process is sensitive to such reflections, reducing the reflections by lowering the reflectivity of materials with good control across wafers and within wafers to under about 15% is essential. In particular, the differences in thickness caused by the polysilicon, metal, and poly/metal stacks has made small feature patterning and critical dimension (CD) control of photoresist very difficult. Such topography causes unpredictable swings in material reflectivity and needs to be reduced or dampened in some way in order to reduce semiconductor device size. Non-uniformities occurring when the dielectric layer undergoes CMP can increase the total reflectivity from the dielectric to the photoresist during photolithography and cause further disruptions in patterning. It is well known that thinner photoresists provide better patterning.
To solve the problem posed by reflectivity, different anti-reflective coatings (ARCs) have been developed which work by phase shift cancellation of specific wavelengths to provide uniform photoresist patterning. These ARCs are specifically designed so that the reflective light from the photoresist/ARC interface is equal in amplitude but opposite in phase to the light reflected from the ARC/reflective layer interface.
It has been found that there are certain line width variations which are due to the ARC not being able to reduce the reflective layer reflectivity to a minimum. The reflectivity causes problems with the photoresist which have been corrected in part by the use of bottom anti-reflective coatings (BARCs) under the photoresists.
Silicon oxynitride (SiON) by itself has been found to be a good BARC material. In essence, the silicon oxynitride BARC serves two functions during semiconductor memory manufacturing: (1) as a hard mask during self-aligned etch (SAE) and during self-aligned-source etch; and (2) as a bottom anti-reflective layer for photolithography at second gate masking.
However, the variations in small feature patterning and CD control have not been eliminated through the use of a SiON BARC.
It appears that during the etching process to etch the SiON not covered by photoresist, variations in the photoresist prevent full etching from occurring and the resulting variation in the SiON is greater than the variation in the photoresist. When subsequent etching occurs with the SiON used as a mask layer, these variations are once again passed down and magnified.
One solution involved compensating for the problem and insuring that the size of the openings at the bottom of the etched region was the correct size. This was accomplished by over-sizing the size of the photolithographic pattern openings. Unfortunately, this results in larger feature sizes, and therefore slower and less efficient semiconductor devices.
In addition, the presence of a BARC typically requires a removal step after it has served its purpose. Because each additional step greatly increases the complexity and speed with which a semiconductor device can be created, the use of a BARC has significant disadvantages.
A method of minimizing the variation in the etching process to allow for smaller semiconductor devices without increasing the number of production steps has long been sought, but has eluded those skilled in the art.
The present invention provides a method of manufacturing a semiconductor with minimized variation in the etching process by using SiON as a bottom antireflective (BARC) layer and hard mask in conjunction with a thin photoresist layer.
The present invention further provides a method of manufacturing a semiconductor with minimized variation in the etching process. Patterning is improved by the use of SiON as a BARC. The thin photoresist layer allows for less variation in the photolithographic process. As a result, there is significantly less variation in the SiON and in turn, there is significantly less variation in later layers in which SiON is used as a hard mask.
The present invention further provides a method of manufacturing a semiconductor without a separate step for BARC removal. After photolithography using a thin photoresist, an improved pattern is etched into the BARC. The BARC is then used as a hard mask making the normal photoresist unnecessary. By the same token, when the dielectric layer is etched, the BARC is used as a hard mask. Because of the thinness of the photoresist, both the photoresist and the BARC layer may be removed as by-products of subsequent etching steps once they are no longer required, therefore eliminating the need for a separate step to remove the remaining BARC material. If the BARC material is not removed during the etching steps, it can be removed during the chemical-mechanical polishing process.
The present invention further provides a method of manufacturing a semiconductor with minimized variation in the etching process and without a separate step for BARC removal. An etch-stop layer is deposited on a semiconductor substrate, a dielectric layer is deposited on top of the etch-stop layer, a BARC is deposed on top of the dielectric layer, and a photoresist layer with a thickness less than the thickness of the dielectric layer is then deposited on top of the BARC. The photoresist is then patterned, photolithographically processed, and developed. The BARC is then etched into the pattern developed on the photoresist. The etched BARC is then used as a hard mask for the patterned etching of the dielectric layer. As a by-product of this etch, the photoresist is removed. The dielectric layer is then used as a mask for the etching of the etch-stop layer. As a by-product of this etch, the BARC is removed.
The present invention further provides a method of manufacturing a semiconductor with minimized variation in the etching process and without a separate step for BARC removal. A nitride etch-stop layer is deposited on a silicon substrate, a layer of silicon oxide is deposited on top of the nitride etch-stop layer, a silicon oxynitride layer is deposited on top of the silicon oxide layer, and a photoresist layer with a thickness less than the thickness of the silicon oxide layer is then deposited on top of the silicon oxynitride layer. The photoresist is then patterned, photolithographically processed, and developed. The silicon oxynitride layer is then etched into the pattern developed on the photoresist. The etched silicon oxynitride layer is then used as a hard mask for the patterned etching of the silicon oxide layer. As a by-product of this etch, the photoresist is removed. The silicon oxide layer is then used as a mask for the etching of the nitride etch-stop layer. As a by-product of this etch, the silicon oxynitride layer is removed.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.